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Single, Low Voltage Digitally Controlled Potentiometer (XDCPTM)
ISL23415
The ISL23415 is a volatile, low voltage, low noise, low power, SPITM bus, 256 taps, single digitally controlled potentiometer (DCP), which integrates DCP core, wiper switches and control logic on a monolithic CMOS integrated circuit. The digitally controlled potentiometer is implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the SPI bus interface. The potentiometer has an associated volatile Wiper Register (WR) that can be directly written to and read by the user. The contents of the WR controls the position of the wiper. When powered on, the ISL23415's wiper will always commence at mid-scale (128 tap position). The low voltage, low power consumption, and small package of the ISL23415 make it an ideal choice for use in battery operated equipment. In addition, the ISL23415 has a VLOGIC pin allowing down to 1.2V bus operation, independent from the VCC value. This allows for low logic levels to be connected directly to the ISL23415 without passing through a voltage level shifter. The DCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.
Features
* 256 resistor taps * SPI serial interface - No additional level translator for low bus supply - Daisy Chaining of multiple DCP * Wiper resistance: 70 typical @ VCC = 3.3V * Shutdown Mode - forces the DCP into an end-to-end open circuit and RW is shorted to RL internally * Power-on preset to mid-scale (128 tap position) * Standby current <2.5A max * Shutdown current <2A * Power supply - VCC = 1.7V to 5.5V analog power supply - VLOGIC = 1.2V to 5.5V SPI bus/logic power supply * DCP terminal voltage from 0V to VCC * 10k, 50k or 100k total resistance * Extended industrial temperature range: -40C to +125C * 10 Ld MSOP or 10 Ld TQFN packages * Pb-free (RoHS compliant)
Applications
* Power supply margining * RF power amplifier bias compensation * LCD bias compensation * Gain adjustment in battery powered instruments * Portable medical equipment calibration
10000
VREF
8000 RESISTANCE ()
6000
ISL23415
4000
+ ISL28114
VREF_M
2000
0
0
50
100
150
200
250
TAP POSITION (DECIMAL)
FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP POSITION, 10k
FIGURE 2. VREF ADJUSTMENT
December 15, 2010 FN7780.0
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2010. All Rights Reserved Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.
ISL23415 Block Diagram
VLOGIC VCC
SCK SDI SDO CS I/O BLOCK LEVEL SHIFTER
POWER-UP INTERFACE, CONTROL AND STATUS LOGIC
RH
WR VOLATILE REGISTER AND WIPER CONTROL CIRCUITRY
RL RW GND
Pin Configurations
ISL23415 (10 LD MSOP) TOP VIEW
VLOGIC SCK SDO SDI CS 1 2 3 4 5 O 10 9 8 7 6 GND VCC RH RW RL
Pin Description
MSOP 1 2 3 4 5 TQFN 10 1 2 3 4 5 6 7 8 9 SYMBOL VLOGIC SCK SDO SDI CS RL RW RH VCC GND DESCRIPTION SPI bus/logic supply. Range 1.2V to 5.5V Logic Pin - Serial bus clock input Logic Pin - Serial bus data output (configurable) Logic Pin - Serial bus data input Logic Pin - Active low Chip Select DCP "low" terminal DCP wiper terminal DCP "high" terminal Analog power supply. Range 1.7V to 5.5V Ground pin
ISL23415 (10 LD TQFN) TOP VIEW
10 VLOGIC
6 7 8 9
9 8 7 6 GND VCC RH RW
O SCK SDO SDI CS 1 2 3 4
10
2
RL
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FN7780.0 December 15, 2010
ISL23415 Ordering Information
PART NUMBER (Note 5) ISL23415TFUZ (Notes 1, 3) ISL23415UFUZ (Notes 1, 3) ISL23415WFUZ (Notes 1, 3) ISL23415TFRUZ-T7A (Notes 2, 4) ISL23415TFRUZ-TK (Notes 2, 4) ISL23415UFRUZ-T7A (Notes 2, 4) ISL23415UFRUZ-TK (Notes 2, 4) ISL23415WFRUZ-T7A (Notes 2, 4) ISL23415WFRUZ-TK (Notes 2, 4) NOTES: 1. Add "-T*" suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. Please refer to TB347 for details on reel specifications. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 5. For Moisture Sensitivity Level (MSL), please see device information page for ISL23415. For more information on MSL please see techbrief TB363. PART MARKING 3415T 3415U 3415W HE HE HD HD HC HC RESISTANCE OPTION (k) 100 50 10 100 100 50 50 10 10 TEMP. RANGE (C) -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 PACKAGE (Pb-free) 10 Ld MSOP 10 Ld MSOP 10 Ld MSOP 10 Ld TQFN 2.1x1.6 10 Ld TQFN 2.1x1.6 10 Ld TQFN 2.1x1.6 10 Ld TQFN 2.1x1.6 10 Ld TQFN 2.1x1.6 10 Ld TQFN 2.1x1.6 PKG. DWG. # M10.118 M10.118 M10.118 L10.2.1x1.6A L10.2.1x1.6A L10.2.1x1.6A L10.2.1x1.6A L10.2.1x1.6A L10.2.1x1.6A
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ISL23415
Absolute Maximum Ratings
Supply Voltage Range VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V VLOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Voltage on any DCP Terminal Pin . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Voltage on any Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Wiper Current IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6mA ESD Rating Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . .6.5kV CDM Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . . . . . . . . 1kV Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . . 200V Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . 100mA @ +125C
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) 10 Ld MSOP Package (Note 6, 7). . . . . . . . 170 70 10 Ld TQFN Package (Note 6, 7) . . . . . . . 145 90 Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +125C VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7V to 5.5V VLOGIC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2V to 5.5V DCP Terminal Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to VCC Max Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 6. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 7. For JC, the "case temp" location is the center top of the package.
Analog Specifications
SYMBOL RTOTAL
VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40C to +125C. TEST CONDITIONS W option U option T option MIN (Note 20) TYP (Note 8) 10 50 100 -20 W option U option T option 2 175 85 70 0 70 VCC 200 +20 MAX (Note 20) UNITS k k k % ppm/C ppm/C ppm/C V
PARAMETER RH to RL resistance
RH to RL resistance tolerance End-to-End Temperature Coefficient
VRH, VRL RW
DCP terminal voltage Wiper resistance
VRH or VRL to GND RH - floating, VRL = 0V, force IW current to the wiper, IW = (VCC - VRL)/RTOTAL, VCC = 2.7V to 5.5V VCC = 1.7V
580 22/22/32 -0.4 <0.1 120 190 220 -65 -75 0.4
pF A nV/Hz nV/Hz nV/Hz dB dB
CH/CL/CW Terminal capacitance ILkgDCP Noise Leakage on DCP pins Resistor noise density
See "DCP Macro Model" on page 8. Voltage at pin from GND to VCC Wiper at middle point, W option Wiper at middle point, U option Wiper at middle point, T option
Feed Thru PSRR
Digital feedthrough from bus to wiper Power Supply Reject Ratio
Wiper at middle point Wiper output change if VCC change 10%; wiper at middle point
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ISL23415
Analog Specifications
SYMBOL VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40C to +125C. (Continued) TEST CONDITIONS MIN (Note 20) TYP (Note 8) MAX (Note 20) UNITS
PARAMETER
VOLTAGE DIVIDER MODE (0V @ RL; VCC @ RH; measured at RW, unloaded)
INL (Note 13) Integral non-linearity, Guaranteed monotonic W option U, T option DNL (Note 12) Differential non-linearity, Guaranteed monotonic W option U, T option FSerror (Note 11) Full-scale error W option U, T option ZSerror (Note 10) Zero-scale error W option U, T option TCV (Note 14) Ratiometric temperature coefficient W option, Wiper Register set to 80 hex U option, Wiper Register set to 80 hex T option, Wiper Register set to 80 hex Large signal wiper settling time fcutoff -3dB cutoff frequency From code 0 to FF hex Wiper at middle point W option Wiper at middle point U option Wiper at middle point T option -1.0 -0.5 -1 -0.4 -3.5 -2 0 0 0.5 0.15 0.4 0.1 -2 -0.5 2 0.4 8 4 2.3 300 1200 250 120 +1.0 +0.5 +1 +0.4 0 0 3.5 2 LSB (Note 9) LSB (Note 9) LSB (Note 9) LSB (Note 9) LSB (Note 9) LSB (Note 9) LSB (Note 9) LSB (Note 9) ppm/C ppm/C ppm/C ns kHz kHz kHz
RHEOSTAT MODE (Measurements between RW and RL pins with RH not connected, or between RW and RH with RL not connected)
RINL (Note 18) Integral non-linearity, Guaranteed monotonic W option; VCC = 2.7V to 5.5V W option; VCC = 1.7V U, T option; VCC = 2.7V to 5.5V U, T option; VCC = 1.7V RDNL (Note 17) Differential non-linearity, Guaranteed monotonic W option; VCC = 2.7V to 5.5V W option; VCC = 1.7V U, T option; VCC = 2.7V to 5.5V U, T option; VCC = 1.7V -0.5 -1 -1.0 -2.0 1 10.5 0.3 2.1 0.4 0.6 0.15 0.35 +0.5 +1 +1.0 +2.0 MI (Note 15) MI (Note 15) MI (Note 15) MI (Note 15) MI (Note 15) MI (Note 15) MI (Note 15) MI (Note 15)
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ISL23415
Analog Specifications
SYMBOL Roffset (Note 16) VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40C to +125C. (Continued) TEST CONDITIONS W option; VCC = 2.7V to 5.5V W option; VCC = 1.7V U, T option; VCC = 2.7V to 5.5V U, T option; VCC = 1.7V TCR (Note 19) Resistance temperature coefficient W option; Wiper register set between 32 hex and FF hex U option; Wiper register set between 32 hex and FF hex T option; Wiper register set between 32 hex and FF hex 0 MIN (Note 20) 0 TYP (Note 8) 3 6.3 0.5 1.1 220 100 75 2 MAX (Note 20) 5.5 UNITS MI (Note 15) MI (Note 15) MI (Note 15) MI (Note 15) ppm/C ppm/C ppm/C
PARAMETER Offset, wiper at 0 position
Operating Specifications
SYMBOL ILOGIC PARAMETER
VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40C to +125C. TEST CONDITIONS VLOGIC = 5.5V, VCC = 5.5V, fSCK = 5MHz (for SPI active read and write) VLOGIC = 1.2V, VCC = 1.7V, fSCK = 1MHz (for SPI active read and write) MIN (Note 20) TYP (Note 8) MAX (Note 20) 1.5 30 100 10 1 0.5 1.5 1 1.3 0.4 0.7 0.5 -0.4 <0.1 1.5 1.5 0.01 50 0.4 UNITS mA A A A A A A A A A A A A s s V/ms
VLOGIC supply current (write/read)
ICC
VCC supply current (write/read)
VLOGIC = 5.5V, VCC = 5.5V VLOGIC = 1.2V, VCC = 1.7V
ILOGIC SB
VLOGIC standby current
VLOGIC = 5.5V, VCC = 5.5V, SPI interface in standby VLOGIC = 1.2V, VCC = 1.7V, SPI interface in standby
ICC SB
VCC standby current
VLOGIC = 5.5V, VCC = 5.5V, SPI interface in standby VLOGIC = 1.2V, VCC = 1.7V, SPI interface in standby
ILOGIC SHDN VLOGIC shutdown current
VLOGIC = 5.5V, VCC = 5.5V, SPI interface in standby VLOGIC = 1.2V, VCC = 1.7V, SPI interface in standby
ICC SHDN
VCC shutdown current
VLOGIC = VCC = 5.5V, SPI interface in standby VLOGIC = 1.2V, VCC = 1.7V, SPI interface in standby
ILkgDig tDCP tShdnRec
Leakage current, at pins CS, SDO, SDI, SCK Voltage at pin from GND to VLOGIC Wiper response time DCP recall time from shutdown mode CS rising edge to wiper new position CS rising edge to wiper recalled position and RH connection Ramp monotonic at any level
VCC, VLOGIC VCC, VLOGIC ramp rate Ramp
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ISL23415
Serial Interface Specification
SYMBOL VIL VIH Hysteresis VOL Rpu (Note 19) Cpin fSCK tCYC tWH tWL tLEAD tLAG tSU tH tRI tFI tDIS tSO tV tHO tRO tFO tCS NOTES: 8. Typical values are for TA = +25C and 3.3V supply voltages. 9. LSB = [V(RW)255 - V(RW)0]/255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 10. ZS error = V(RW)0/LSB. 11. FS error = [V(RW)255 - VCC]/LSB. 12. DNL = [V(RW)i - V(RW)i-1]/LSB-1, for i = 1 to 255. i is the DCP register setting. 14. 13. INL = [V(RW)i - i * LSB - V(RW)0]/LSB for i = 1 to 255 Max ( V ( RW ) i ) - Min ( V ( RW ) i ) 10 6 for i = 16 to 255 decimal, T = -40C to +125C. Max( ) is the maximum value of the wiper voltage TC V = ----------------------------------------------------------------------------- x --------------------V ( RWi ( +25C ) ) +165C and Min( ) is the minimum value of the wiper voltage over the temperature range. PARAMETER Input LOW Voltage Input HIGH Voltage SDI and SCK Input Buffer Hysteresis SDO Output Buffer LOW Voltage SDO pull-up resistor off-chip SCK, SDO, SDI, CS Pin Capacitance SCK Frequency VLOGIC = 1.7V to 5.5V VLOGIC = 1.2V to 1.6V SPI clock cycle time SPI clock high time SPI clock low time Lead time Lag time SDI, SCK and CS input setup time SDI, SCK and CS input hold time SDI, SCK and CS input rise time SDI, SCK and CS input fall time SDO output Disable time SDO output setup time SDO output valid time SDO output hold time SDO output rise time SDO output fall time CS deselect time VLOGIC 1.7V VLOGIC 1.7V VLOGIC 1.7V VLOGIC 1.7V VLOGIC 1.7V VLOGIC 1.7V VLOGIC 1.7V VLOGIC 1.7V VLOGIC 1.7V VLOGIC 1.7V VLOGIC 1.7V VLOGIC 1.7V VLOGIC 1.7V Rpu = 1.5k, Cbus = 30pF Rpu = 1.5k, Cbus = 30pF 2 200 100 100 250 250 50 50 10 10 0 50 150 0 60 60 20 100 VLOGIC > 2V VLOGIC < 2V IOL = 3mA, VLOGIC > 2V IOL = 1.5mA, VLOGIC < 2V Maximum is determined by tRO and tFO with maximum bus load Cb = 30pF, fSCK = 5MHz 10 5 1
For SCK, SDI, SDO, CS Unless Otherwise Noted.
TEST CONDITIONS MIN (Note 20) -0.3 0.7 x VLOGIC 0.05 x VLOGIC 0.1 x VLOGIC 0 0.4 0.2 x VLOGIC 1.5 V V k pF MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s TYP (Note 8) MAX (Note 20) 0.3 x VLOGIC VLOGIC+ 0.3 UNITS V V V
15. MI = |RW255 - RW0|/255. MI is a minimum increment. RW255 and RW0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively. 16. Roffset = RW0/MI, when measuring between RW and RL. Roffset = RW255/MI, when measuring between RW and RH. 17. RDNL = (RWi - RWi-1)/MI -1, for i = 16 to 255. 18. RINL = [RWi - (MI * i) - RW0]/MI, for i = 16 to 255. 19. [ Max ( Ri ) - Min ( Ri ) ] 10 for i = 16 to 255, T = -40C to +125C. Max( ) is the maximum value of the resistance and Min( ) is the TC R = ------------------------------------------------------ x --------------------Ri ( +25C ) +165C minimum value of the resistance over the temperature range.
6
20. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
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ISL23415 DCP Macro Model
RTOTAL RH CH CW CL 22pF RL
22pF RW
32pF
Timing Diagrams
Input Timing
tCS CS tLEAD SCK tSU SDI MSB tH tWL tCYC ... tWH ... tLAG
tFI LSB
tRI
SDO
Output Timing
CS
SCK tSO SDO MSB tV SDI ADDR tHO
... tDIS ... LSB
XDCPTM Timing (for All Load Instructions)
CS tDCP SCK ... ...
SDI
MSB
LSB
VW
SDO
*When CS is HIGH SDO at Z or Hi-Z state
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FN7780.0 December 15, 2010
ISL23415 Typical Performance Curves
0.4 0.30
0.2
DNL (LSB) DNL (LSB)
0.15
0
0
-0.2
-0.15
-0.4 0 50 100 150 200 250 TAP POSITION (DECIMAL)
-0.30
0
50
100
150
200
250
TAP POSITION (DECIMAL)
FIGURE 3. 10k DNL vs TAP POSITION, VCC = 5V
FIGURE 4. 50k DNL vs TAP POSITION, VCC = 5V
0.4
0.30
0.2
INL (LSB) INL (LSB)
0.15
0
0
-0.2
-0.15
-0.4 0 50 100 150 200 250 TAP POSITION (DECIMAL)
-0.30 0 50 100 150 200 250 TAP POSITION (DECIMAL)
FIGURE 5. 10k INL vs TAP POSITION, VCC = 5V
FIGURE 6. 50k INL vs TAP POSITION, VCC = 5V
0.4
0.30
0.2
RDNL (MI) RDNL (MI)
0.15
0
0
-0.2
-0.15
-0.4
0
50
100
150
200
250
-0.30
0
50
TAP POSITION (DECIMAL)
100 150 TAP POSITION (DECIMAL)
200
250
FIGURE 7. 10k RDNL vs TAP POSITION, VCC = 5V
FIGURE 8. 50k RDNL vs TAP POSITION, VCC = 5V
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ISL23415 Typical Performance Curves
0.6 0.4 0.15 0.2
RINL (MI) RINL (MI)
(Continued)
0.30
0 -0.2
0
-0.15 -0.4 -0.6 -0.30
0
50
100
150
200
250
0
50
100
150
200
250
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 9. 10k RINL vs TAP POSITION, VCC = 5V
FIGURE 10. 50k RINL vs TAP POSITION, VCC = 5V
70 +125C 60
WIPER RESISTANCE ()
60 +125C 50 +25C
WIPER RESISTANCE ()
+25C
50 40 30 20 10 0 0 50
40 30 20 10 0
-40C
-40C
100 150 TAP POSITION (DECIMAL)
200
250
0
50
100
150
200
250
TAP POSITION (DECIMAL)
FIGURE 11. 10k WIPER RESISTANCE vs TAP POSITION, VCC = 5V
FIGURE 12. 50k WIPER RESISTANCE vs TAP POSITION, VCC = 5V
300 250 200 150 100 50 0 15
70 60 50
TCv (ppm/C)
TCv (ppm/C)
40 30 20 10 0 15
65
115
165
215
65
115
165
215
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 13. 10k TCv vs TAP POSITION
FIGURE 14. 50k TCv vs TAP POSITION
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ISL23415 Typical Performance Curves
600 500 150
TCr (ppm/C) TCr (ppm/C)
(Continued)
200
400 300 200 100 0 15
100
50
65
115
165
215
0 15
65
115
165
215
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 15. 10k TCr vs TAP POSITION
FIGURE 16. 50k TCr vs TAP POSITION
35 30 25
TCv (ppm/C)
120
90
TCr (ppm/C)
20 15 10 5 0 15
60
30
65
115
165
215
0 15
65
TAP POSITION (DECIMAL)
115 165 TAP POSITION (DECIMAL)
215
FIGURE 17. 100k TCv vs TAP POSITION
FIGURE 18. 100k TCr vs TAP POSITION
SCK CLOCK
RW PIN 10mV/DIV 1s/DIV 20mV/DIV 5s/DIV
FIGURE 19. WIPER DIGITAL FEEDTHROUGH
FIGURE 20. WIPER TRANSITION GLITCH
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ISL23415 Typical Performance Curves
1V/DIV 1s/DIV
(Continued)
1V/DIV 0.1s/DIV
VRW
CS RISING EDGE
FIGURE 21. WIPER LARGE SIGNAL SETTLING TIME
FIGURE 22. POWER-ON START-UP IN VOLTAGE DIVIDER MODE
CH1: 0.5V/DIV, 0.2s/DIV RH PIN CH2: 0.2V/DIV, 0.2s/DIV RW PIN
STANDBY CURRENT ICC (A)
1.2 1.0 0.8 0.6 0.4 0.2 0 -40 VCC = 1.7V, VLOGIC = 1.2V
VCC = 5.5V, VLOGIC = 5.5V
RTOTAL = 10k -3dB FREQUENCY = 1.4MHz AT MIDDLE TAP
-15
10
35
60
85
110
TEMPERATURE (C)
FIGURE 23. 10k -3dB CUT OFF FREQUENCY
FIGURE 24. STANDBY CURRENT vs TEMPERATURE
Functional Pin Description
Potentiometers Pins
RH AND RL
The high (RH) and low (RL) terminals of the ISL23415 are equivalent to the fixed terminals of a mechanical potentiometer. The RH and RL are referenced to the relative position of the wiper and not the voltage potential on the terminals. With the WR register set to 255 decimal, the wiper will be closest to RH, and with the WR register set to 0, the wiper is closest to RL. RW The RW is the wiper terminal, and it is equivalent to the moveable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WR register.
Bus Interface Pins
SERIAL CLOCK (SCL)
This input is the serial clock of the SPI serial interface.
SERIAL DATA INPUT (SDI)
The SDI is a serial data input pin for SPI interface. It receives operation code, wiper address and data from the SPI remote host device. The data bits are shifted in at the rising edge of the serial clock SCK, while the CS input is low.
SERIAL DATA OUTPUT (SDO)
The SDO is a serial data output pin. During a read cycle, the data bits are shifted out on the falling edge of the serial clock SCK and will be available to the master on the following rising edge of SCK. The output type is configured through ACR[1] bit for Push-Pull or Open Drain operation. Default setting for this pin is Push-Pull. An
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ISL23415
external pull-up resistor is required for Open Drain output operation. When CS is HIGH, the SDO pin is in tri-state (Z) or high-tri-state (Hi-Z) depends on the selected configuration. Register (ACR) at address 10h contains information and control bits described in Table 2.
TABLE 1. MEMORY MAP ADDRESS (hex) 10 0 VOLATILE ACR WR TABLE 2. ACCESS CONTROL REGISTER (ACR) BIT # NAME 7 0 6 SHDN 5 0 4 0 3 0 2 0 1 SDO 0 0 DEFAULT SETTING (hex) 40 80
CHIP SELECT (CS)
CS LOW enables the ISL23415, placing it in the active power mode. A HIGH to LOW transition on CS is required prior to the start of any operation after power-up. When CS is HIGH, the ISL23415 is deselected and the SDO pin is at high impedance, and the device will be in the standby state.
Principles of Operation
The ISL23415 is an integrated circuit incorporating one DCP with its associated registers and an SPI serial interface providing direct communication between a host and the potentiometer. The resistor array is comprised of individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The electronic switches on the device operate in a "make before break" mode when the wiper changes tap positions. Voltage at any DCP pins, RH, RL or RW, should not exceed VCC level at any conditions during power-up and normal operation. The VLOGIC pin needs to be connected to the SPI bus supply which allows reliable communication with the wide range of microcontrollers and independent of the VCC level. This is extremely important in systems where the digital supply has lower levels than the analog supply.
The SHDN bit (ACR[6]) disables or enables Shutdown mode. When this bit is 0, i.e., each DCP is forced to end-to-end open circuit and each RW is shorted to RL as shown in Figure 25. Default value of the SHDN bit is 1.
RH
RW
RL
FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE
DCP Description
Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin of the DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by the 8-bit volatile Wiper Register (WR). When the WR of a DCP contains all zeroes (WR[7:0] = 00h), its wiper terminal (RW) is closest to its "Low" terminal (RL). When the WR register of a DCP contains all ones (WR[7:0] = FFh), its wiper terminal (RW) is closest to its "High" terminal (RH). As the value of the WR increases from all zeroes (0) to all ones (255 decimal), the wiper moves monotonically from the position closest to RL to the position closest to RH. At the same time, the resistance between RW and RL increases monotonically, while the resistance between RH and RW decreases monotonically. While the ISL23415 is being powered up, the WR is reset to 80h (128 decimal), which locates RW roughly at the center between RL and RH. The WR can be read or written to directly using the SPI serial interface as described in the following sections.
The SDO bit (ACR[1]) configures type of SDO output pin. The default value of SDO bit is 0 for Push-Pull output. The SDO pin can be configured as Open Drain output for some applications. In this case, an external pull-up resistor is required, reference the "Serial Interface Specification" on page 7.
SPI Serial Interface
The ISL23415 supports an SPI serial protocol, mode 0. The device is accessed via the SDI input and SDO output with data clocked in on the rising edge of SCK, and clocked out on the falling edge of SCK. CS must be LOW during communication with the ISL23415. The SCK and CS lines are controlled by the host or master. The ISL23415 operates only as a slave device. All communication over the SPI interface is conducted by sending the MSB of each byte of data first.
Protocol Conventions
The SPI protocol contains Instruction Byte followed by one or more Data Bytes. A valid Instruction Byte contains instruction as the three MSBs, with the following five register address bits (see Table 3). The next byte sent to the ISL23415 is the Data Byte.
TABLE 3. INSTRUCTION BYTE FORMAT BIT # 7 I2 6 I1 5 I0 4 R4 3 R3 2 R2 1 R1 0 R0
Memory Description
The ISL23415 contains two volatile 8-bit registers: the Wiper Register (WR) and the Access Control Register (ACR). Memory map of ISL23415 is in Table 1. The Wiper Register WR at address 0 contains current wiper position of the DCP. The Access Control 13
Table 4 contains a valid instruction set for ISL23415. If the [R4:R0] bits are zero, then the read or write is to the WR register. If the [R4:R0] are 10000, then the operation is to the ACR.
FN7780.0 December 15, 2010
ISL23415
Write Operation
A write operation to the ISL23415 is a two or more bytes operation. It requires first, the CS transition from HIGH-to-LOW. Then host send a valid Instruction Byte, followed by one or more Data Bytes to SDI pin. The host terminates the write operation by pulling the CS pin from LOW-to-HIGH. Instruction is executed on rising edge of CS.
Read Operation
A Read operation to the ISL23415 is a four byte operation. It requires first, the CS transition from HIGH-to-LOW. Then host send a valid Instruction Byte, followed by "dummy" Data Byte, NOP Instruction Byte and another "dummy" Data Byte to SDI pin. The SPI host receives the Instruction Byte (instruction code + register address) and requested Data Byte from SDO pin on the rising edge of SCK during third and fourth bytes respectively. The host terminates the read by pulling the CS pin from LOW-to-HIGH (see Figure 27).
TABLE 4. INSTRUCTION SET INSTRUCTION SET I2 0 0 0 1 1 I1 0 0 1 0 1 I0 0 1 1 0 0 R4 X X X R4 R4 R3 X X X R3 R3 R2 X X X R2 R2 R1 X X X R1 R1 R0 X X X R0 R0 NOP ACR READ ACR WRTE WR or ACR READ WR or ACR WRTE OPERATION
where X means "do not care".
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCK
SDI
WR INSTRUCTION
ADDR
DATA BYTE
SDO
FIGURE 26. TWO BYTE WRITE SEQUENCE
CS
1
8
16
24
32
SCK
SDI
RD
ADDR
NOP
SDO
RD
ADDR
READ DATA
FIGURE 27. FOUR BYTE READ SEQUENCE
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FN7780.0 December 15, 2010
ISL23415 Applications Information
Communicating with ISL23415
Communication with ISL23415 proceeds using SPI interface through the ACR (address 10000b) and WR (addresses 00000b) registers. The wiper of the potentiometer is controlled by the WR register. Writes and reads can be made directly to these register to control and monitor the wiper position. The first part starts by HIGH-to-LOW transition on CS line, followed by N two bytes read instruction on SDI line with reversed chain access sequence: the instruction byte + dummy data byte for the last DCP in chain is going first, followed by LOW-to-HIGH transition on CS line. The read instructions are executed during second part of read sequence. It also starts by HIGH-to-LOW transition on CS line, followed by N number of two bytes NOP instructions on SDI line and LOW-to-HIGH transition of CS. The data is read on every even byte during second part of read sequence while every odd byte contains code 111b followed by address from which the data is being read.
Daisy Chain Configuration
When application needs more than one ISL23415, it can communicate with all of them without additional CS lines by daisy chaining the DCPs as shown on Figure 28. In Daisy Chain configuration, the SDO pin of the previous chip is connected to the SDI pin of the following chip, and each CS and SCK pins are connected to the corresponding microcontroller pins in parallel, like regular SPI interface implementation. The Daisy Chain configuration can also be used for simultaneous setting of multiple DCPs. Note, the number of daisy chained DCPs is limited only by the driving capabilities of SCK and CS pins of microcontroller; for larger number of SPI devices buffering of SCK and CS lines is required.
Wiper Transition
When stepping up through each tap in voltage divider mode, some tap transition points can result in noticeable voltage transients, or overshoot/undershoot, resulting from the sudden transition from a very low impedance "make" to a much higher impedance "break within a short period of time (<1s). There are several code transitions such as 0Fh to 10h, 1Fh to 20h,..., EFh to FFh, which have higher transient glitch. Note, that all switching transients will settle well within the settling time as stated in the datasheet. A small capacitor can be added externally to reduce the amplitude of these voltage transients, but that will also reduce the useful bandwidth of the circuit, thus may not be a good solution for some applications. It may be a good idea, in that case, to use fast amplifiers in a signal chain for fast recovery.
Daisy Chain Write Operation
The write operation starts by HIGH-to-LOW transition on CS line, followed by N number of two bytes write instructions on SDI line with reversed chain access sequence: the instruction byte + data byte for the last DCP in chain is going first, as shown in Figure 29, where N is a number of DCPs in chain. The serial data is going through DCPs from DCP0 to DCP(N-1) as follow: DCP0 --> DCP1 --> DCP2 --> ... --> DCP(N-1). The write instruction is executed on the rising edge of CS for all N DCPs simultaneously.
VLOGIC Requirements
It is recommended to keep VLOGIC powered all the time during normal operation. In a case where turning VLOGIC OFF is necessary, it is recommended to ground the VLOGIC pin of the ISL23415. Grounding the VLOGIC pin or both VLOGIC and VCC does not affect other devices on the same bus. It is good practice to put a 1F capacitor in parallel with 0.1F decoupling capacitor close to the VLOGIC pin.
Daisy Chain Read Operation
The read operation consists of two parts: first, send the read instructions (N two bytes operation) with valid address; second, read the requested data while sending NOP instructions (N two bytes operation) as shown in Figures 30 and 31.
VCC Requirements and Placement
It is recommended to put a 1F capacitor in parallel with 0.1F decoupling capacitor close to the VCC pin.
N DCP IN A CHAIN CS SCK MOSI MISO C CS SCK SDI SDO DCP0 CS SCK SDI SDO DCP1 CS SCK SDI SDO DCP2 DCP(N-1) CS SCK SDI SDO
FIGURE 28. DAISY CHAIN CONFIGURATION
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FN7780.0 December 15, 2010
ISL23415
CS
SCK 16 CLKLS SDI SDO 0 SDO 1 WR D C P2 16 CLKS WR WR D C P1 D C P2 WR WR WR 16 CLKS D C P0 D C P1 D C P2
SDO 2
FIGURE 29. DAISY CHAIN WRITE SEQUENCE OF N = 3 DCP
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCK
SDI
INSTRUCTION
ADDR
DATA IN
SDO
DATA OUT
FIGURE 30. TWO BYTE READ INSTRUCTION
CS
SCK 16 CLKS SDI RD DCP2 16 CLKS RD DCP1 16 CLKS RD DCP0 16 CLKS NOP 16 CLKS NOP 16 CLKS NOP
SDO
DCP2 OUT
DCP1 OUT
DCP0 OUT
FIGURE 31. DAISY CHAIN READ SEQUENCE OF N = 3 DCP
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FN7780.0 December 15, 2010
ISL23415 Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev.
DATE 12/15/10 REVISION FN7780.0 Initial Release CHANGE
Products
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For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com
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FN7780.0 December 15, 2010
ISL23415
Mini Small Outline Plastic Packages (MSOP)
N
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1 -BE
INCHES SYMBOL MIN 0.037 0.002 0.030 0.007 0.004 0.116 0.116 0.187 0.016 10 0.003 0.003 5o 0o 15o 6o MAX 0.043 0.006 0.037 0.011 0.008 0.120 0.120 0.199 0.028 A
ABC
MILLIMETERS MIN 0.94 0.05 0.75 0.18 0.09 2.95 2.95 4.75 0.40 10 0.07 0.07 5o 0o 15o 6o MAX 1.10 0.15 0.95 0.27 0.20 3.05 3.05 5.05 0.70 NOTES 9 3 4 6 7 Rev. 0 12/02
INDEX AREA
12 TOP VIEW
0.20 (0.008)
A1 A2
4X
0.25 (0.010) GAUGE PLANE SEATING PLANE -C-
R1 R
b c D E1
A
A2
4X
L L1
e E L L1 N R
0.020 BSC
0.50 BSC
A1
-He D
b
0.10 (0.004) -A0.20 (0.008)
C
SEATING PLANE
0.037 REF
0.95 REF
C a C L E1
C
R1
SIDE VIEW
-B-
0.20 (0.008)
CD
END VIEW
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension "D" does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (.004) at seating Plane. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
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FN7780.0 December 15, 2010
ISL23415
Package Outline Drawing
L10.2.1x1.6A
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 5, 3/10
8. PIN 1 INDEX AREA 2.10 B 1 A PIN #1 ID 8. 0.10 MIN. 1.60 10 1 0.05 MIN.
4 4X 0.20 MIN.
5
0.80 0.10 2X TOP VIEW BOTTOM VIEW 9 6X 0.50 6 10 X 0.20 4 0.10 M C A B MC SEE DETAIL "X" PACKAGE OUTLINE MAX. 0.55 0.10 C C (0.10 MIN.) (2.00) SIDE VIEW (1.30) SEATING PLANE 0.08 C 10X 0.40
(10 X 0.20)
(0.05 MIN) 1
(10X 0.60)
(0.80)
C (6X 0.50 ) (2.50)
0 . 125 REF
0-0.05 TYPICAL RECOMMENDED LAND PATTERN DETAIL "X"
NOTES: 1. 2. 3. 4. Dimensioning and tolerancing conform to ASME Y14.5M-1994. All Dimensions are in millimeters. Angles are in degrees. Dimensions in ( ) for Reference Only. Unless otherwise specified, tolerance : Decimal 0.05 Lead width dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. Maximum package warpage is 0.05mm. Maximum allowable burrs is 0.076mm in all directions. Same as JEDEC MO-255UABD except: No lead-pull-back, MIN. Package thickness = 0.45 not 0.50mm Lead Length dim. = 0.45mm max. not 0.42mm. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
5. 6. 7.
8.
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FN7780.0 December 15, 2010

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